Hitherto, there has been proposed a parallel data processor in which a plurality of PE of the identical structure are arranged in a two-dimensional lattice configuration, each of said PE being connected in an adjoining relation and operated by an identical instruction provided by an external control section and each PE providing therein a means for storing the status signals and a means for selecting one of the operations by the status signal so that each input signal from the adjoining PE and the data signals stored in the PE are transferred into the computing system just as disclosed in the Japanese laid-open patent publication No. 56-123069.
An arrangement of PE according to the foregoing conventional parallel data processor is shown in FIG. 8 which comprises a PE 2, a selector 21 for selecting data from the adjacent PE 2, a register file 22, a two-input ALU 23, a selector 24 for selecting an input to the two-input ALU 23 and a selector 25 for selecting data to the adjacent PE 2.
Operation of the PE in the conventional parallel data processor will now be described hereinbelow. In the operation within the PE, two data are taken up from the register file 22 and operated in the two-input ALU 23, a result of which is stored in the register file 22 repeatedly. When data transmission should be conducted between the PEs 2, the data is read out from the register file 22 of the PE 2 on the data-feeding side and is fed through each selector 24, 25 to the adjacent PE 2. If the PE 2 having received the data is a relevant PE, then the data is transmitted through each selector 21, 24 and the 2-input ALU 23 to the register file 22 for its storage. If the PE 2 has received the data for mere transfer purpose, on the contrary, the data is transmitted through each selector 21, 25 to the adjacent PE 2.
In this way, the data transmission between the PEs 2 may be conducted on the same periodic basis using the register file 22 and the 2-input ALU 23.
In the PE 2 thus constructed in the conventional parallel data processor, however, the data transmission betwee the PEs 2 requires synchronization to the operation in the PE 2 using the register file 22 and the 2-input ALU 23 and the PE 2 cannot be operated for other purposes during the data transmission between the PEs 2.
In other words, the synchronization in the PEs 2 is determined by the read-out and write-in of the register file 22 as a computing center and by the operation time in the 2-input ALU 23, while the data transmission between the PEs, which should be completed at a higher speed, spends a longer wasteful time. Further, during the data transmission between the PEs, the register file 22 associated with such data transmission may prohibit another operation in the PE.
For this reason, the parallel data processor including a plurality of PEs connected in the two-dimensional lattice pattern is excellent in its extendability and may be readily improved in its performance, but has a problem of delayed data transmission requiring a longer time therefor between the PEs.
Accordingly, an object of the invention is to solve the above problem and to provide a parallel data processor having ability of transmitting the data between the PEs at a higher speed by means of asynchronous data transmission relative to operation in the PE and of concurrent data transmission independently from the operation in the PE.